The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2013

Filed:

Aug. 05, 2009
Applicants:

Kiichiro Higaki, Kanagawa-ken, JP;

Koichi Sugihara, Kanagawa-ken, JP;

Katsuya Murakami, Tokyo, JP;

Shigenori Sawachi, Kanagawa-ken, JP;

Mitsuru Oida, Tokyo, JP;

Inventors:

Kiichiro Higaki, Kanagawa-ken, JP;

Koichi Sugihara, Kanagawa-ken, JP;

Katsuya Murakami, Tokyo, JP;

Shigenori Sawachi, Kanagawa-ken, JP;

Mitsuru Oida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.


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