The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2013
Filed:
May. 03, 2011
Jon Mclachlan, San Francisco, CA (US);
Ganna Zaks, Mountain View, CA (US);
Julien Lerouge, Santa Clara, CA (US);
Pierre Betouin, Boulogne, FR;
Augustin J. Farrugia, Cupertino, CA (US);
Gideon M. Myles, San Jose, CA (US);
Cédric Tessier, Paris, FR;
Jon McLachlan, San Francisco, CA (US);
Ganna Zaks, Mountain View, CA (US);
Julien Lerouge, Santa Clara, CA (US);
Pierre Betouin, Boulogne, FR;
Augustin J. Farrugia, Cupertino, CA (US);
Gideon M. Myles, San Jose, CA (US);
Cédric Tessier, Paris, FR;
Apple Inc., Cupertino, CA (US);
Abstract
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating a computer program. A system configured to practice the method identifies a set of executable instructions at a first location in an instruction section of the computer program and identifies a second location in a data section of the computer program. Then the system moves the set of executable instructions to the second location and patches references in the computer program to the set of executable instructions to point to the second location. The instruction section of the computer program can be labeled as _TEXT,_text and the data section of the computer program is labeled as _DATA,_data. The set of executable instructions can include one or more non-branching instructions optionally followed by a branching instruction. The placement of the first and second locations can be based on features of a target computing architecture, such as cache size.