The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2013
Filed:
Jul. 28, 2011
Tetsuya Hirose, Hyogo, JP;
Yuji Osaki, Hyogo, JP;
Tetsuya Hirose, Hyogo, JP;
Yuji Osaki, Hyogo, JP;
Semiconductor Technology Academic Research Center, Kanagawa, JP;
Abstract
A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.