The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2013
Filed:
Mar. 20, 2012
Susumu Obata, Kanagawa-ken, JP;
Kazuhito Higuchi, Kanagawa-ken, JP;
Hideo Nishiuchi, Hyogo-ken, JP;
Akiya Kimura, Kanagawa-ken, JP;
Toshiya Nakayama, Kanagawa-ken, JP;
Yoshiaki Sugizaki, Kanagawa-ken, JP;
Akihiro Kojima, Kanagawa-ken, JP;
Yosuke Akimoto, Kanagawa-ken, JP;
Susumu Obata, Kanagawa-ken, JP;
Kazuhito Higuchi, Kanagawa-ken, JP;
Hideo Nishiuchi, Hyogo-ken, JP;
Akiya Kimura, Kanagawa-ken, JP;
Toshiya Nakayama, Kanagawa-ken, JP;
Yoshiaki Sugizaki, Kanagawa-ken, JP;
Akihiro Kojima, Kanagawa-ken, JP;
Yosuke Akimoto, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
According to an embodiment, a semiconductor light emitting device includes a stacked body, first and second electrodes, first and second interconnections, first and second pillars and a first insulating layer. The stacked body includes first and second semiconductor layers and a light emitting layer. The first and second electrodes are connected to the first and second semiconductor layers respectively. The first and second interconnections are connected to the first and second electrode respectively. The first and second pillars are connected to the first and second interconnections respectively. The first insulating layer is provided on the interconnections and the pillars. The first and second pillars have first and second monitor pads exposed in a surface of the first insulating layer. The first and second interconnections have first and second bonding pads exposed in a side face connected with the surface of the first insulating layer.