The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

Dec. 10, 2008
Applicants:

Spiros Kalogeropulos, Los Gatos, CA (US);

Yonghong Song, Palo Alto, CA (US);

Partha P. Tirumalai, Fremont, CA (US);

Inventors:

Spiros Kalogeropulos, Los Gatos, CA (US);

Yonghong Song, Palo Alto, CA (US);

Partha P. Tirumalai, Fremont, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for automatic efficient parallelization of code combined with hardware transactional memory support. A software application may contain a transaction synchronization region (TSR) utilizing lock and unlock transaction synchronization function calls for a shared region of memory within a shared memory. The TSR is replaced with two portions of code. The first portion comprises hardware transactional memory primitives in place of lock and unlock function calls. Also, the first portion ensures no other transaction is accessing the shared region without disabling existing hardware transactional memory support. The second portion performs a fail routine, which utilizes lock and unlock transaction synchronization primitives in response to an indication that a failure occurs within said first portion.


Find Patent Forward Citations

Kalogeropulos, Spiros. (2013). Compiler implementation of lock/unlock using hardware transactional memory (U.S. Patent No. 8612929). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8612929

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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