The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

Sep. 30, 2010
Applicants:

Ho-fan Kang, Irvine, CA (US);

Cliff Pajaro, Costa Mesa, CA (US);

Inventors:

Ho-Fan Kang, Irvine, CA (US);

Cliff Pajaro, Costa Mesa, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of the invention are directed to systems and methods for improving wear leveling performance in solid-state memory. The embodiments described herein make more consistent the number of wear leveling operations that need to be performed, so that sudden spikes in the number wear leveling operations may be reduced in solid-state memory. In one embodiment, a rule-based wear leveling approach is used to spread out the execution of wear leveling operations that otherwise would have been triggered in clusters. Under the rule-based approach, wear leveling is periodically triggered by a specified interval of erase counts associated with a unit of solid-state memory such as a group of blocks, rather than by a threshold based on erase counts.


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Kang, Ho-Fan. (2013). System and method for improving wear-leveling performance in solid-state memory (U.S. Patent No. 8612804). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8612804

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