The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2013
Filed:
May. 14, 2008
Johannes Boonstra, Deurne, NL;
Sundaravaradan Rangarajan, Bangalore, IN;
Rajendra Kumar, Bangalore, IN;
Johannes Boonstra, Deurne, NL;
Sundaravaradan Rangarajan, Bangalore, IN;
Rajendra Kumar, Bangalore, IN;
NXP, B.V., Eindhoven, NL;
Abstract
A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (), a write pointer circuit () clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit () which has its write pointer address incremented synchronously with the write pointer circuit (), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (). A comparator () compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.