The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2013
Filed:
Mar. 24, 2010
Gi Nam Wang, Suwon-Si, KR;
Sang Chul Park, Yongin-Si, KR;
Hyeong Tae Park, Suwon-Si, KR;
UDMTEK Co., Ltd., Gyeonggido, KR;
Abstract
Disclosed are a PLC (Programmable Logic Controller) symbol structure for a PLC code for automatically generating an input/output model, and a simulation apparatus and a simulation method for testing the PLC code using the same. In one embodiment, a computer-readable recording medium records a PLC code including a plurality of PLC symbols, wherein each of the PLC symbols includes a plurality of levels identified by an identifier, and a computer automatically generates an input/output model using the structure of each of the PLC symbols, thereby performing a simulation for testing the PLC code. The PLC symbol structure according to one embodiment systematically contains information required for automatically generating the input/output model, making it possible to automatically generate the input/output model for testing the PLC code in an easier manner without knowledge of simulation and modeling, and reducing the time consumed and the labor required for generating the input/output model.