The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

Jan. 12, 2011
Applicants:

James Plusquellic, Albuquerque, NM (US);

Dhruva J. Acharyya, San Hose, CA (US);

Ryan L. Helinski, Albuquerque, NM (US);

Inventors:

James Plusquellic, Albuquerque, NM (US);

Dhruva J. Acharyya, San Hose, CA (US);

Ryan L. Helinski, Albuquerque, NM (US);

Assignee:

STC.UNM, Albuquerque, NM (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and methods that generates a physical unclonable function ('PUF') security key for an integrated circuit ('IC') through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.


Find Patent Forward Citations

Plusquellic, James. (2013). System and methods for generating unclonable security keys in integrated circuits (U.S. Patent No. 8610454). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8610454

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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