The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2013
Filed:
Aug. 16, 2012
Akira Hokazono, Clifton Park, NY (US);
Akira Hokazono, Clifton Park, NY (US);
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
Structures and methods are presented relating to formation of finFET semiconducting devices. An approach is presented to facilitate formation of a pMOS finFET which can be combined with a nMOS finFET to form a balanced CMOS device. A Si:C layer can be utilized to suppress diffusion of group III and group V impurities, where suppression can utilize interstitial and substitutional phases. A Si:Ge layer can be utilized to facilitate determination of transition between a Si layer and a Si:C layer to enable a finFET to be formed having a required volume of fin material exposed for anticipated operation (e.g., a target Vth) of the finFET device.