The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

May. 27, 2011
Applicant:

Mitsuru Soma, Kumagaya, JP;

Inventor:

Mitsuru Soma, Kumagaya, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween. Then the dummy semiconductor substrate is removed, thereby forming an SOI substrate having the embedded insulation film, the P+ type embedded collector layer, the N type buffer layer, the N type drift layer and so on that are exposed being almost flush with each other on the bottom of the trench. An IGBT and so on are formed on this SOI substrate.


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