The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2013

Filed:

Apr. 30, 2013
Applicant:

Micrel, Inc., San Jose, CA (US);

Inventor:

David R. Zinn, San Jose, CA (US);

Assignee:

Micrel, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/337 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.


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