The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Mar. 30, 2012
Applicants:

Carmelo Ucciardello, Catania, IT;

Antonino Conte, Tremestieri, IT;

Giovanni Matranga, Catania, IT;

Rosario Roberto Grasso, Acicastello, IT;

Inventors:

Carmelo Ucciardello, Catania, IT;

Antonino Conte, Tremestieri, IT;

Giovanni Matranga, Catania, IT;

Rosario Roberto Grasso, Acicastello, IT;

Assignee:

STMicroelectronics S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.


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