The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2013
Filed:
Jun. 06, 2011
Christopher G. Regier, Cedar Park, TX (US);
L. Rolando Ortega-pohlenz, Austin, TX (US);
Christopher G. Regier, Cedar Park, TX (US);
L. Rolando Ortega-Pohlenz, Austin, TX (US);
National Instruments Corporation, Austin, TX (US);
Abstract
A source-measure unit (SMU) may be implemented with digital control loops. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters), and the readings obtained by the ADCs may be compared to a setpoint in a digital loop controller, which may produce an output to drive a DAC (digital-to-analog converter) to maintain the output voltage and/or output current at a desired setpoint. The digital loop controller may also digitally implement simulated resistance with high resolution, accuracy, and range, using Thévenin and Norton power supply models. Simulated resistor values may range from 10Ω to 10Ω for output currents in the 100 mA range, with a sub-200μΩ resolution. The range may be expanded up to 100 kΩ for output currents in the 10 μA range. The Norton and Thévenin implementations may be combined, and a 'pure resistance' mode may be created for simulating any desired resistance value. A variation of the general resistance-simulation technique may also be used to compensate for Common Mode Voltage effects in the current measurement path, providing tighter output and measurement specifications at a lower component cost.