The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Apr. 14, 2006
Applicants:

Hideki Hiromoto, Kyoto, JP;

Sadamasa Fujii, Kyoto, JP;

Tsunemori Yamaguchi, Kyoto, JP;

Inventors:

Hideki Hiromoto, Kyoto, JP;

Sadamasa Fujii, Kyoto, JP;

Tsunemori Yamaguchi, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.


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