The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Sep. 29, 2010
Michael D. Hutton, Mountain View, CA (US);
Gregg William Baeckler, San Jose, CA (US);
Jinyong Yuan, Cupertino, CA (US);
Chris Wysocki, Toronto, CA;
Pouyan Djahani, Toronto, CA;
Michael D. Hutton, Mountain View, CA (US);
Gregg William Baeckler, San Jose, CA (US);
Jinyong Yuan, Cupertino, CA (US);
Chris Wysocki, Toronto, CA;
Pouyan Djahani, Toronto, CA;
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.