The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Dec. 29, 2011
Bogdan I. Georgescu, Colorado Springs, CO (US);
Ryan T. Hirose, Colorado Springs, CO (US);
Bogdan I. Georgescu, Colorado Springs, CO (US);
Ryan T. Hirose, Colorado Springs, CO (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A circuit is configured to supply a first gate voltage (PG) at a first voltage bias (VP) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP) to a second transistor and supplying a second voltage bias (VN) and a second gate voltage (NG) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP) and a third gate voltage (PG) to a fourth transistor, and a fourth voltage bias (VN) and a fourth gate voltage (NG) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN) to a line connecting the third transistor to the fifth transistor.