The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2013

Filed:

Aug. 15, 2007
Applicants:

Tyson J. Bergland, Palo Alto, CA (US);

Craig M. Okruhlica, San Jose, CA (US);

Edward A. Hutchins, Mountain View, CA (US);

Michael J. M. Toksvig, Palo Alto, CA (US);

Justin M. Mahan, Fremont, CA (US);

Inventors:

Tyson J. Bergland, Palo Alto, CA (US);

Craig M. Okruhlica, San Jose, CA (US);

Edward A. Hutchins, Mountain View, CA (US);

Michael J. M. Toksvig, Palo Alto, CA (US);

Justin M. Mahan, Fremont, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 15/80 (2006.01); G09G 5/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.


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