The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Mar. 08, 2007
Katsumi Abe, Kawasaki, JP;
Masafumi Sano, Yokohama, JP;
Ryo Hayashi, Yokohama, JP;
Hideya Kumomi, Tokyo, JP;
Katsumi Abe, Kawasaki, JP;
Masafumi Sano, Yokohama, JP;
Ryo Hayashi, Yokohama, JP;
Hideya Kumomi, Tokyo, JP;
Canon Kabushiki Kaisha, Tokyo, JP;
Abstract
A driving circuit of a display element includes a current source circuit having a first transistor and a holding circuit for holding a gate voltage of the first transistor during a first period at an electric potential corresponding to a constant current to be supplied to the display element, and a control circuit including a second transistor connected in series to the current source circuit and connected in parallel to the display element and the capacitor element whose one terminal is connected to a gate of the second transistor and the other terminal is connected to a line, and controlling the light emission time of the display element by controlling the second transistor during a third period. A constant voltage is applied from the line during the first period. The gray-scale voltage is applied from the line during a second period, and the gate of the second transistor and the one terminal are short-circuited. In addition, an electric charge based on the difference between the gray-scale voltage and the gate voltage of the second transistor is accumulated in the capacitor element, and a sweep voltage is applied during the third period, so that the ON time of the second transistor is controlled.