The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8595562 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 26, 2013

Filed:

Jan. 26, 2011
Applicants:

Takashi Sato, Yokohama, JP;

Toshiaki Saruwatari, Yokohama, JP;

Ken Ryu, Yokohama, JP;

Inventors:

Takashi Sato, Yokohama, JP;

Toshiaki Saruwatari, Yokohama, JP;

Ken Ryu, Yokohama, JP;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.


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Sato, Takashi. (2013). Semiconductor integrated circuit, operating method of semiconductor integrated circuit, and debug system (U.S. Patent No. 8595562). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8595562

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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