The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
Mar. 03, 2008
Yifeng Zhang, San Jose, CA (US);
Peiqi Xuan, Saratoga, CA (US);
Kanyu Cao, Cupertino, CA (US);
Xiaodong Jin, Saratoga, CA (US);
Yifeng Zhang, San Jose, CA (US);
Peiqi Xuan, Saratoga, CA (US);
Kanyu Cao, Cupertino, CA (US);
Xiaodong Jin, Saratoga, CA (US);
Quintic Holdings, George Town, Grand Cayman, KY;
Abstract
In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.