The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
Sep. 25, 2009
Alexander L. Minkin, Los Altos, CA (US);
Steven James Heinrich, Madison, AL (US);
Rajeshwaran Selvanesan, Milpitas, CA (US);
Brett W. Coon, San Jose, CA (US);
Charles Mccarver, Madison, AL (US);
Anjana Rajendran, San Jose, CA (US);
Stewart G. Carlton, Madison, AL (US);
Alexander L. Minkin, Los Altos, CA (US);
Steven James Heinrich, Madison, AL (US);
RaJeshwaran Selvanesan, Milpitas, CA (US);
Brett W. Coon, San Jose, CA (US);
Charles McCarver, Madison, AL (US);
Anjana Rajendran, San Jose, CA (US);
Stewart G. Carlton, Madison, AL (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A 'direct mapped' storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A 'local and global cache' storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.