Method and circuit for efficient caching of reference video data

Abstract

In some embodiments, a video processing system including video processor, an external memory, and an integrated circuit that implements both a memory controller (having embedded intelligence) and an internal memory coupled to the memory controller. The memory controller is configured to pre-cache in the internal memory partial frames of reference video data in the external memory (e.g., N-line slices of M-line reference frames, where M>N), and to respond to requests (e.g., from the video processor) for blocks of reference video data including by determining whether each requested block (or each of at least two portions thereof) has been pre-cached in the internal memory, causing each requested cached block (or portion thereof) to be read from the internal memory, and causing each requested non-cached block (or portion thereof) to be read from the external memory. Preferably, the pre-caching is performed in a predetermined manner independent of which read requests for the reference data are actually asserted, and exploits known correlation between two-dimensional pixel locality of each block ('current block') of data to undergo processing (e.g., decoding) using reference data, two-dimensional pixel locality of each block of reference data that may be requested to process the current block, and probability that each such reference data block will be needed to process the current block. Other aspects are memory controllers for use in such a system and methods performed during operation of any such system or memory controller.