The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
Mar. 19, 2012
Arun Sundaresan Iyer, Karnataka, IN;
Nithin Shetty Kidiyoor, Karnataka, IN;
Shyam Sundaramoorthy, Karnataka, IN;
Ravishankar Karthikeyan, Karnataka, IN;
Arun Sundaresan Iyer, Karnataka, IN;
Nithin Shetty Kidiyoor, Karnataka, IN;
Shyam Sundaramoorthy, Karnataka, IN;
Ravishankar Karthikeyan, Karnataka, IN;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.