The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2013

Filed:

Dec. 11, 2009
Applicants:

Tae-hoon Yang, Yongin, KR;

Han-hee Yoon, Yongin, KR;

Kil-won Lee, Yongin, KR;

Jang-soon Im, Yongin, KR;

Ji-yong Noh, Yongin, KR;

Inventors:

Tae-Hoon Yang, Yongin, KR;

Han-Hee Yoon, Yongin, KR;

Kil-Won Lee, Yongin, KR;

Jang-Soon Im, Yongin, KR;

Ji-Yong Noh, Yongin, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/18 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

An organic light emission diode (OLED) display device and a method of fabricating the same, wherein the OLED display device includes a substrate including a pixel region and a non-pixel region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, and including a channel region and source/drain regions, a gate electrode disposed to correspond to the channel region of the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, source/drain electrodes electrically connected to the source/drain regions of the semiconductor layer, and an interlayer insulating layer insulating the gate electrode from the source/drain electrodes, wherein areas of the buffer layer, the gate insulating layer and the interlayer insulating layer that are on the non-pixel region, respectively, are removed, and the partially removed area is 8% to 40% of a panel area.


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