The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
Nov. 09, 2012
International Business Machines Corporation, Armonk, NY (US);
Manjul Bhushan, Hopewell Junction, NY (US);
Eric J. Fluhr, Round Rock, TX (US);
Stephen G. Shuma, Underhill, VT (US);
Debjit Sinha, Wappingers Falls, NY (US);
Chandramouli Visweswariah, Croton on Hudson, NY (US);
James D. Warnock, Somers, NY (US);
Michael H. Wood, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An approach for performing device-based random variability modeling in timing analysis of a digital integrated circuit having a gate-level design and a device-level custom design is described. In one embodiment, an algorithm is derived from results of simulating the operational behavior of a representative digital integrated circuit. A timing analysis is performed on the device-level custom design part of the digital integrated circuit to obtain device-level random variability sensitivity values. A gate-level characterization is performed on the gate-level design part of the digital integrated circuit to obtain logic gate random variability sensitivity values. A timing analysis is performed on the digital integrated circuit as a function of both the device-level random variability sensitivity values and the logic gate random variability sensitivity values.