The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
Oct. 01, 2010
Robert E. Cox, Somers, CT (US);
James A. Gosse, Storrs, CT (US);
Kimberly K. Sendlein, Marlborough, CT (US);
David S. Harman, Simsbury, CT (US);
Robert E. Cox, Somers, CT (US);
James A. Gosse, Storrs, CT (US);
Kimberly K. Sendlein, Marlborough, CT (US);
David S. Harman, Simsbury, CT (US);
Hamilton Sundstrand Corporation, Windsor Locks, CT (US);
Abstract
An error detection and correction (EDAC) circuit mitigates the effect of single event upsets (SEU) events in a redundant memory system. The EDAC circuit includes a first input for receiving first data and parity information stored by a first memory device and a second input for receiving second data and parity information stored by a second memory device. First parity check logic calculates parity for the received first data and parity information. Second parity check logic calculates parity for the received second data and parity information. Bit comparison logic detects differences between the first data and the second data, and between the first parity information and the second parity information. Based on the parity check calculated for the first and second data, and the bit comparison, data select logic selects either the first data or the second data for provision to a data bus.