Memory device having multi-port memory cell with expandable port configuration

Abstract

A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.