The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
Aug. 25, 2011
Jae-joon Kim, Yorktown Heights, NY (US);
Yu-shiang Lin, Elmsford, NY (US);
Liang-teck Pang, White Plains, NY (US);
Joel A. Silberman, Somers, NY (US);
Jae-Joon Kim, Yorktown Heights, NY (US);
Yu-Shiang Lin, Elmsford, NY (US);
Liang-Teck Pang, White Plains, NY (US);
Joel A. Silberman, Somers, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.