The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2013
Filed:
Nov. 14, 2006
Applicants:
Toshinori Sueyoshi, Kumamoto, JP;
Masahiro Iida, Kumamoto, JP;
Motoki Amagasaki, Kumamoto, JP;
Kazuhiko Taketa, Gifu, JP;
Taketo Heishi, Osaka, JP;
Nobuharu Suzuki, Tokyo, JP;
Inventors:
Toshinori Sueyoshi, Kumamoto, JP;
Masahiro Iida, Kumamoto, JP;
Motoki Amagasaki, Kumamoto, JP;
Kazuhiko Taketa, Gifu, JP;
Taketo Heishi, Osaka, JP;
Nobuharu Suzuki, Tokyo, JP;
Assignee:
Semiconductor Technology Academic Research Center, Yokohama, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract
A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.