The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2013

Filed:

Jul. 27, 2012
Applicants:

Josephine B. Chang, Mahopac, NY (US);

Wilfried E. Haensch, Somers, NY (US);

Fei Liu, Mt. Kisco, NY (US);

Zihong Liu, White Plains, NY (US);

Inventors:

Josephine B. Chang, Mahopac, NY (US);

Wilfried E. Haensch, Somers, NY (US);

Fei Liu, Mt. Kisco, NY (US);

Zihong Liu, White Plains, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
Abstract

A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.


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