The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2013

Filed:

Mar. 23, 2012
Applicants:

Jennifer E. Appleyard, Burlington, VT (US);

John E. Barth, Jr., Williston, VT (US);

John B. Deforge, Barre, VT (US);

Herbert L. Ho, New Windsor, NY (US);

Babar A. Khan, Ossining, NY (US);

Kirk D. Peterson, Jericho, VT (US);

Andrew A. Turner, Underhill, VT (US);

Inventors:

Jennifer E. Appleyard, Burlington, VT (US);

John E. Barth, Jr., Williston, VT (US);

John B. DeForge, Barre, VT (US);

Herbert L. Ho, New Windsor, NY (US);

Babar A. Khan, Ossining, NY (US);

Kirk D. Peterson, Jericho, VT (US);

Andrew A. Turner, Underhill, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.


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