The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Nov. 02, 2010
Michael J. Osborn, Hollis, NH (US);
Michael J. Tresidder, Newmarket, CA;
Aaron J. Grenat, Austin, TX (US);
Joseph Kidd, Hudson, MA (US);
Priyank Parakh, Arlington, MA (US);
Steven J. Kommrusch, Fort Collins, CO (US);
Michael J. Osborn, Hollis, NH (US);
Michael J. Tresidder, Newmarket, CA;
Aaron J. Grenat, Austin, TX (US);
Joseph Kidd, Hudson, MA (US);
Priyank Parakh, Arlington, MA (US);
Steven J. Kommrusch, Fort Collins, CO (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.