The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Aug. 29, 2011
Wendy A. Belluomini, San Jose, CA (US);
Binny S. Gill, San Jose, CA (US);
James L. Hafner, San Jose, CA (US);
Steven R. Hetzler, Los Altos, CA (US);
Venu G. Nayar, San Jose, CA (US);
Daniel F. Smith, Felton, CA (US);
Krishnakumar Rao Surugucchi, Fremont, CA (US);
Wendy A. Belluomini, San Jose, CA (US);
Binny S. Gill, San Jose, CA (US);
James L. Hafner, San Jose, CA (US);
Steven R. Hetzler, Los Altos, CA (US);
Venu G. Nayar, San Jose, CA (US);
Daniel F. Smith, Felton, CA (US);
Krishnakumar Rao Surugucchi, Fremont, CA (US);
International Business Machines, New York, NY (US);
Abstract
Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.