The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Jan. 06, 2011
Kyung-ho Park, Cheonan-si, KR;
So-young Kim, Jeju-si, KR;
SI Hyun Ahn, Cheonan-si, KR;
Dong Hee Shin, Seoul, KR;
Hyung-jun Park, Seongnam-si, KR;
Soo-hyun Kim, Chungju-si, KR;
Kyung-Ho Park, Cheonan-si, KR;
So-Young Kim, Jeju-si, KR;
Si Hyun Ahn, Cheonan-si, KR;
Dong Hee Shin, Seoul, KR;
Hyung-Jun Park, Seongnam-si, KR;
Soo-Hyun Kim, Chungju-si, KR;
Samsung Display Co., Ltd., , KR;
Abstract
A liquid crystal display, the liquid crystal display comprises a plurality of gate lines which includes a first gate line, a transformation gate line, and a second gate line; a data line; and a pixel, wherein the pixel includes a first liquid crystal capacitor which includes a first sub-pixel electrode and a common electrode and a second liquid crystal capacitor which includes a second sub-pixel electrode and a common electrode; a first switching element connected to the first gate line, the data line, and the first sub-pixel electrode; a second switching element connected to the first gate line, the data line, and the second sub-pixel electrode; a third switching element connected to the transformation gate line and the second switching element; a transformation capacitor which includes a first terminal connected to the second gate line and a second terminal connected to the third switching element; and a first period where a gate-on voltage Von is applied to the first gate line and a second period where the gate-on voltage Von is applied to the transformation gate line do not overlap each other and, a gate-off voltage Voff is applied to the second gate line during the second period.