The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2013

Filed:

Dec. 24, 2011
Applicant:

Paul Mateman, Millingen aan de Rijn, NL;

Inventor:

Paul Mateman, Millingen aan de Rijn, NL;

Assignee:

ST-Ericsson SA, Plan-les-Ouates, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Sample-and-hold circuits typically operate at maximum speed when the sampling phase is much shorter than the holding phase. Thus, a device driving the sampling capacitor is disconnected most of the time. Methods and apparatus use the holding phase to store the full charge required by the sampling capacitor to track the amplifier output in at least two 'boost' capacitors configured such that when the sampling capacitor is switched to the driver, the boost capacitors are also switched to the driver. Thus, the sampling capacitor is almost instantly charged to the required voltage, and the driver needs to supply only any remaining 'error' charge, avoiding delays due to driver output slewing.


Find Patent Forward Citations

Mateman, Paul. (2013). Sample-and-hold circuit arrangement (U.S. Patent No. 8581636). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8581636

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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