The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Jan. 17, 2011
Atsuhito Murai, Osaka, JP;
Shinya Tanaka, Osaka, JP;
Hideki Kitagawa, Osaka, JP;
Hajime Imai, Osaka, JP;
Mitsunori Imade, Osaka, JP;
Tetsuo Kikuchi, Osaka, JP;
Kazunori Morimoto, Osaka, JP;
Junya Shimada, Osaka, JP;
Jun Nishimura, Osaka, JP;
Atsuhito Murai, Osaka, JP;
Shinya Tanaka, Osaka, JP;
Hideki Kitagawa, Osaka, JP;
Hajime Imai, Osaka, JP;
Mitsunori Imade, Osaka, JP;
Tetsuo Kikuchi, Osaka, JP;
Kazunori Morimoto, Osaka, JP;
Junya Shimada, Osaka, JP;
Jun Nishimura, Osaka, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
The circuit board () of the present invention includes a plurality of transistor elements provided on a single insulating substrate () for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT () having a channel layer () formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT () having a channel layer () formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT () and the a-Si TFT () is a bottom-gate transistor.