The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2013

Filed:

Feb. 13, 2012
Applicants:

Erina Yamada, Komaki, JP;

Hironori Sato, Kasugai, JP;

Inventors:

Erina Yamada, Komaki, JP;

Hironori Sato, Kasugai, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B29C 65/52 (2006.01); B32B 37/02 (2006.01); B32B 37/12 (2006.01); B32B 38/10 (2006.01); B32B 38/04 (2006.01); B32B 43/00 (2006.01); C09J 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a reliable multilayer wiring substrate at a relatively low cost having little or no warpage or distortion is provided. In certain embodiments an insulation core made of an insulation material that is more rigid than that of resin insulation layers is prepared. A through hole is formed through core upper and lower surfaces of the insulation core, and a through hole conductor is formed therein. A plate-like substrate is prepared, and resin insulation layers and at least one conductor layer are laminated on the substrate to form a first buildup layer. The insulation core is laminated on the first buildup layer so as to electrically connect the conductor layer and the through hole conductor. Resin insulation layers and at least one conductor layer are then laminated on the insulation core. Lastly, the substrate is separated from the first buildup layer to yield a multilayer wiring substrate.


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