The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Jul. 26, 2012
Derick G. Behrends, Rochester, MN (US);
Todd A. Christensen, Rochester, MN (US);
Travis R. Hebig, Rochester, MN (US);
Michael Launsbach, Rochester, MN (US);
Derick G. Behrends, Rochester, MN (US);
Todd A. Christensen, Rochester, MN (US);
Travis R. Hebig, Rochester, MN (US);
Michael Launsbach, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, system and computer program product are provided for implementing multiple mask lithography timing variation mitigation for a multiple mask polysilicon (PC) process. An application specific integrated circuit (ASIC) library includes at least one circuit device for a first mask, and at least one circuit device for a second mask. Critical hold time paths and critical setup time paths are identified in a circuit design. For critical hold time paths, circuit devices in the critical hold time paths are placed on a single mask of either the first mask or the second mask. For critical setup time paths, path delays are reduced by providing a mixture of circuit devices on the first mask and the second mask.