The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Feb. 17, 2005
Wolfgang Fey, Niederhausen, DE;
Micha Heinz, Darmstadt, DE;
Adrian Traskov, Steinbach, DE;
Frank Michel, Rosbach v.d. Höhe, DE;
Wolfgang Fey, Niederhausen, DE;
Micha Heinz, Darmstadt, DE;
Adrian Traskov, Steinbach, DE;
Frank Michel, Rosbach v.d. Höhe, DE;
Continental Teves AG & Co., OHG, Frankfurt, DE;
Abstract
Disclosed is a method of improving the immunity to interference of an integrated circuit () having error signals transferred between a microprocessor chip or multiple processor μC () and an additional component (). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller () or microprocessor module and an additional component () having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (') one after the other through at least one error line ().