The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Sep. 09, 2009
Graham R. Leach, Swindon, GB;
Gordon A. Wilson, Swindon, GB;
Rolf Sundblad, Ljungsbro, SE;
CSR Technology Inc., Sunnyvale, CA (US);
Abstract
A PLL circuit () for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump () is arranged to generate an output signal based on the up and down signals and a loop filter () is arranged to generate a frequency-control signal based on the output signal of the charge pump (). Furthermore, a VCO () is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO () is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz. A programmable first frequency divider () is arranged to generate the pixel-clock signal by frequency division of the oscillating signal, and a programmable second frequency divider () is arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.