The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2013

Filed:

May. 16, 2011
Applicants:

Kenneth Crandall, Sunnyvale, CA (US);

Michael Brosnan, Fremont, CA (US);

Sam Sen LI, Santa Cruz, CA (US);

Inventors:

Kenneth Crandall, Sunnyvale, CA (US);

Michael Brosnan, Fremont, CA (US);

Sam Sen Li, Santa Cruz, CA (US);

Assignee:

Pixart Imaging, Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/045 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed are various embodiments of a capacitive touchscreen or touch panel system comprising a controller operably connected to a first plurality of drive electrodes and a second plurality of sense electrodes. The controller includes a noise disruption detector circuit, a user noise source detector/anticipator circuit, clock control logic circuitry operably connected to the noise disruption detector circuit and to the user noise source detector/anticipator circuit, at least one static-clocked digital filter circuit operably connected to and controlled by the clock control logic circuitry, a central processing unit (CPU) operably connected to the clock control logic circuitry, firmware operably connected to the CPU; and touch position circuitry configured to deliver signals indicative of touch positions on the touchscreen to a host controller. The controller is configured to employ at least one of the CPU and the firmware to cause the clock control logic circuitry to inhibit operation of the digital filter circuit in response to a signal representative of excessive noise levels being provided by either the noise disruption detector circuit or the user noise source detector/anticipator circuit.


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