The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Aug. 25, 2011
Jae-joon Kim, Yorktown Heights, NY (US);
Yu-shiang Lin, Elmsford, NY (US);
Liang-teck Pang, White Plains, NY (US);
Joel A. Silberman, Somers, NY (US);
Jae-Joon Kim, Yorktown Heights, NY (US);
Yu-Shiang Lin, Elmsford, NY (US);
Liang-Teck Pang, White Plains, NY (US);
Joel A. Silberman, Somers, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.