The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2013
Filed:
Jul. 25, 2008
Chantal Arena, Mesa, AZ (US);
Christiaan J. Werkhoven, Gilbert, AZ (US);
Ronald Thomas Bertram, Jr., Mesa, AZ (US);
Ed Lindow, Scottsdale, AZ (US);
Subhash Mahajan, Tempe, AZ (US);
Ranjan Datta, Tempe, AZ (US);
Rahul Ajay Trivedi, Tempe, AZ (US);
Ilsu Han, Tempe, AZ (US);
Chantal Arena, Mesa, AZ (US);
Christiaan J. Werkhoven, Gilbert, AZ (US);
Ronald Thomas Bertram, Jr., Mesa, AZ (US);
Ed Lindow, Scottsdale, AZ (US);
Subhash Mahajan, Tempe, AZ (US);
Ranjan Datta, Tempe, AZ (US);
Rahul Ajay Trivedi, Tempe, AZ (US);
Ilsu Han, Tempe, AZ (US);
Soitec, Bernin, FR;
Arizona Board of Regents for and on Behalf of Arizona State University, Scottsdale, AZ (US);
Abstract
This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.