The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2013
Filed:
Dec. 20, 2010
Sivakumar Ardhanari, Chennai, IN;
Vardhamana G Hegde, Chennai, IN;
Madhanagopalan Sambath Kumar, Chennai, IN;
Balakuteswar V Voleti, Chennai, IN;
Sivakumar Ardhanari, Chennai, IN;
Vardhamana G Hegde, Chennai, IN;
Madhanagopalan Sambath Kumar, Chennai, IN;
Balakuteswar V Voleti, Chennai, IN;
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
An on-chip testing unit can be implemented in an integrated circuit (e.g., a SoC) to validate the operation of cache memories associated with a processor of the integrated circuit. For each testing instruction to be executed by the processor for testing a cache memory, the testing unit can intercept information (e.g., address, data, and/or control signals) generated by the processor in response to executing the instruction. The testing unit can determine whether information generated by the processor matches corresponding expected information associated with the instruction. This can enable the testing unit to determine whether the processor can correctly identify an address from which the next instruction is to be fetched, can ensure consistency between data in the cache memories and persistent storage devices, and whether the processor is operating as expected. An error notification can be generated if the information generated by the processor does not match the expected information.