The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2013
Filed:
Mar. 16, 2009
Ali Rostampisheh, San Diego, CA (US);
Raghu N. Challa, San Diego, CA (US);
Iwen Yao, San Diego, CA (US);
Davie J. Santos, Encinitas, CA (US);
Mrinal M. Nath, San Diego, CA (US);
Ali RostamPisheh, San Diego, CA (US);
Raghu N. Challa, San Diego, CA (US);
Iwen Yao, San Diego, CA (US);
Davie J. Santos, Encinitas, CA (US);
Mrinal M. Nath, San Diego, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.