The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2013

Filed:

Dec. 05, 2011
Applicants:

Shiming He, Shanghai, CN;

Liqian Chen, Shanghai, CN;

Cong Yao, Shanghai, CN;

Xiang LI, Shanghai, CN;

Yu Liu, Shanghai, CN;

Jiayin LU, Shanghai, CN;

Inventors:

Shiming He, Shanghai, CN;

Liqian Chen, Shanghai, CN;

Cong Yao, Shanghai, CN;

Xiang Li, Shanghai, CN;

Yu Liu, Shanghai, CN;

Jiayin Lu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.


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