The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2013
Filed:
May. 15, 2007
Oleg Drapkin, Richmond Hill, CA;
Grigori Temkine, Markham, CA;
Marcus NG, Toronto, CA;
Kevin Yikai Liang, Cupertino, CA (US);
Arvind Bomdica, Fremont, CA (US);
Siji Menokki Kandiyil, San Jose, CA (US);
Ming SO, Danville, CA (US);
Samu Suryanarayana, Sunnyvale, CA (US);
Oleg Drapkin, Richmond Hill, CA;
Grigori Temkine, Markham, CA;
Marcus Ng, Toronto, CA;
Kevin Yikai Liang, Cupertino, CA (US);
Arvind Bomdica, Fremont, CA (US);
Siji Menokki Kandiyil, San Jose, CA (US);
Ming So, Danville, CA (US);
Samu Suryanarayana, Sunnyvale, CA (US);
ATI Technologies ULC, Markham, Ontario, CA;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.