The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2013
Filed:
Apr. 03, 2012
Hidetomo Kobayashi, Isehara, JP;
Masami Endo, Isehara, JP;
Yutaka Shionoiri, Isehara, JP;
Hiroki Dembo, Isehara, JP;
Tatsuji Nishijima, Hadano, JP;
Kazuaki Ohshima, Isehara, JP;
Seiichi Yoneda, Atsugi, JP;
Jun Koyama, Sagamihara, JP;
Hidetomo Kobayashi, Isehara, JP;
Masami Endo, Isehara, JP;
Yutaka Shionoiri, Isehara, JP;
Hiroki Dembo, Isehara, JP;
Tatsuji Nishijima, Hadano, JP;
Kazuaki Ohshima, Isehara, JP;
Seiichi Yoneda, Atsugi, JP;
Jun Koyama, Sagamihara, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;
Abstract
A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.