The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2013
Filed:
Nov. 03, 2011
Yin Qian, Milpitas, CA (US);
Hsin-chih Tai, San Jose, CA (US);
Keh-chiang Ku, Cupertino, CA (US);
Vincent Venezia, Los Gatos, CA (US);
Duli Mao, Sunnyvale, CA (US);
Wei Zheng, Los Gatos, CA (US);
Howard E. Rhodes, San Martin, CA (US);
Yin Qian, Milpitas, CA (US);
Hsin-Chih Tai, San Jose, CA (US);
Keh-Chiang Ku, Cupertino, CA (US);
Vincent Venezia, Los Gatos, CA (US);
Duli Mao, Sunnyvale, CA (US);
Wei Zheng, Los Gatos, CA (US);
Howard E. Rhodes, San Martin, CA (US);
OmniVision Technologies, Inc., Santa Clara, CA (US);
Abstract
Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.